Rev. 1.50, 10/04, page 175 of 448
8.5 Cache Operation Instruction
8.5.1 Coherency between Cache and External Memory
Coherency between cache and external memory should be assured by software. In the SH-4A, the
following six instructions are supported for cache operations. Details of these instructions are
given in section 10, Instruction Descriptions.
• Operand cache invalidate instruction: OCBI @Rn
Operand cache invalidation (no write-back)
• Operand cache purge instruction: OCBP @Rn
Operand cache invalidation (with write-back)
• Operand cache write-back instruction: OCBWB @Rn
Operand cache write-back
• Operand cache allocate instruction: MOVCA.L R0,@Rn
Operand cache allocation
• Instruction cache invalidate instruction: ICBI @Rn
Instruction cache invalidation
• Operand access synchronization instruction: SYNCO
Wait for data transfer completion
The operand cache can receive "PURGE" and "FLUSH" transaction from SuperHyway bus to
control the cache coherency. Since the address used by the PURGE and FLUSH transaction is a
physical address, the following restrictions occur to avoid cache synonym problem in MMU
enable mode.
• 1Kbyte page size cannot be used.
PURGE transaction: When the operand cache is enabled, the PURGE transaction checks the
operand cache and invalidates the hit entry. If the invalidated entry is dirty, the data is written back
to the external memory. If the transaction is not hit to the cache, it is no-operation.
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