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Rev. 1.50, 10/04, page 33 of 448

Table 3.5 Arithmetic Operation Instructions

Instruction Operation Instruction Code Privileged T Bit New

ADD Rm,Rn Rn + Rm → Rn

0011nnnnmmmm1100

— — —

ADD #imm,Rn Rn + imm → Rn

0111nnnniiiiiiii

— — —

ADDC Rm,Rn Rn + Rm + T → Rn,

carry → T

0011nnnnmmmm1110

— Carry —

ADDV Rm,Rn Rn + Rm → Rn,

overflow → T

0011nnnnmmmm1111

— Overflow —

CMP/EQ #imm,R0 When R0 = imm, 1 → T

Otherwise, 0 → T

10001000iiiiiiii

— Comparison

result

—

CMP/EQ Rm,Rn When Rn = Rm, 1 → T

Otherwise, 0 → T

0011nnnnmmmm0000

— Comparison

result

—

CMP/HS Rm,Rn When Rn ≥ Rm (unsigned),

1 → T

Otherwise, 0 → T

0011nnnnmmmm0010

— Comparison

result

—

CMP/GE Rm,Rn When Rn ≥ Rm (signed),

1 → T

Otherwise, 0 → T

0011nnnnmmmm0011

— Comparison

result

—

CMP/HI Rm,Rn When Rn > Rm (unsigned),

1 → T

Otherwise, 0 → T

0011nnnnmmmm0110

— Comparison

result

—

CMP/GT Rm,Rn When Rn > Rm (signed),

1 → T

Otherwise, 0 → T

0011nnnnmmmm0111

— Comparison

result

—

CMP/PZ Rn When Rn ≥ 0, 1 → T

Otherwise, 0 → T

0100nnnn00010001

— Comparison

result

—

CMP/PL Rn When Rn > 0, 1 → T

Otherwise, 0 → T

0100nnnn00010101

— Comparison

result

—

CMP/STR Rm,Rn When any bytes are equal,

1 → T

Otherwise, 0 → T

0010nnnnmmmm1100

— Comparison

result

—

DIV1 Rm,Rn 1-step division (Rn ÷ Rm)

0011nnnnmmmm0100

— Calculation

result

—

DIV0S Rm,Rn MSB of Rn → Q,

MSB of Rm → M, M^Q → T

0010nnnnmmmm0111

— Calculation

result

—

DIV0U 0 → M/Q/T

0000000000011001

— 0 —

DMULS.L Rm,Rn Signed,

Rn × Rm → MAC,

32 × 32 → 64 bits

0011nnnnmmmm1101

— — —

DMULU.L Rm,Rn Unsigned,

Rn × Rm → MAC,

32 × 32 → 64 bits

0011nnnnmmmm0101

— — —

Brand	Renesas
Model	SuperH SH-4A
Category	Computer Hardware
Language	English

Renesas SuperH SH-4A User Manual

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