Rev. 1.50, 10/04, page 19 of 448
Table 2.2 Bit Allocation for FPU Exception Handling
Field Name
FPU
Error (E)
Invalid
Operation (V)
Division
by Zero (Z)
Overflow
(O)
Underflow
(U)
Inexact
(I)
Cause FPU exception
cause field
Bit 17 Bit 16 Bit 15 Bit 14 Bit 13 Bit 12
Enable FPU exception
enable field
None Bit 11 Bit 10 Bit 9 Bit 8 Bit 7
Flag FPU exception flag
field
None Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
Floating-Point Communication Register (FPUL) (32 bits, Initial Value = Undefined):
Information is transferred between the FPU and CPU via FPUL.
2.3 Memory-Mapped Registers
Some control registers are mapped to the following memory areas. Each of the mapped registers
has two addresses.
H'1C00 0000 to H'1FFF FFFF
H'FC00 0000 to H'FFFF FFFF
These two areas are used as follows.
• H'1C00 0000 to H'1FFF FFFF
This area must be accessed using the address translation function of the MMU.
Setting the page number of this area to the corresponding field of the TLB enables access to a
memory-mapped register.
The operation of an access to this area without using the address translation function of the
MMU is not guaranteed.
• H'FC00 0000 to H'FFFF FFFF
Access to area H'FC00 0000 to H'FFFF FFFF in user mode will cause an address error.
Memory-mapped registers can be referenced in user mode by means of access that involves
address translation.
Note: Do not access addresses to which registers are not mapped in either area. The operation of
an access to an address with no register mapped is undefined. Also, memory-mapped
registers must be accessed using a fixed data size. The operation of an access using an
invalid data size is undefined.
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