Renesas SuperH SH-4A - Table of Contents

Rev. 1.50, 10/04, page ix of xx
Contents
Section 1 Overview............................................................................................1
1.1 Features............................................................................................................................. 1
1.2 Changes from SH-4 to SH-4A .......................................................................................... 4
Section 2 Programming Model ..........................................................................7
2.1 Data Formats.....................................................................................................................7
2.2 Register Descriptions........................................................................................................ 8
2.2.1 Privileged Mode and Banks ................................................................................. 8
2.2.2 General Registers................................................................................................. 11
2.2.3 Floating-Point Registers.......................................................................................12
2.2.4 Control Registers ................................................................................................. 14
2.2.5 System Registers.................................................................................................. 16
2.3 Memory-Mapped Registers...............................................................................................19
2.4 Data Formats in Registers................................................................................................. 20
2.5 Data Formats in Memory.................................................................................................. 20
2.6 Processing States...............................................................................................................21
2.7 Usage Notes ...................................................................................................................... 22
2.7.1 Notes on Self-Modified Codes............................................................................. 22
Section 3 Instruction Set ....................................................................................23
3.1 Execution Environment ....................................................................................................23
3.2 Addressing Modes ............................................................................................................ 25
3.3 Instruction Set ................................................................................................................... 29
Section 4 Pipelining ...........................................................................................43
4.1 Pipelines............................................................................................................................43
4.2 Parallel-Executability........................................................................................................ 54
4.3 Issue Rates and Execution Cycles..................................................................................... 56
Section 5 Exception Handling ...........................................................................65
5.1 Summary of Exception Handling...................................................................................... 65
5.2 Register Descriptions........................................................................................................ 65
5.2.1 TRAPA Exception Register (TRA) ..................................................................... 66
5.2.2 Exception Event Register (EXPEVT).................................................................. 67
5.2.3 Interrupt Event Register (INTEVT)..................................................................... 68
5.3 Exception Handling Functions.......................................................................................... 69
5.3.1 Exception Handling Flow .................................................................................... 69
5.3.2 Exception Handling Vector Addresses ................................................................ 69
5.4 Exception Types and Priorities ......................................................................................... 70