Rev. 1.50, 10/04, page x of xx
5.5 Exception Flow................................................................................................................. 72
5.5.1 Exception Flow.................................................................................................... 72
5.5.2 Exception Source Acceptance.............................................................................. 73
5.5.3 Exception Requests and BL Bit ........................................................................... 74
5.5.4 Return from Exception Handling......................................................................... 74
5.6 Description of Exceptions................................................................................................. 75
5.6.1 Resets................................................................................................................... 75
5.6.2 General Exceptions.............................................................................................. 77
5.6.3 Interrupts.............................................................................................................. 91
5.6.4 Priority Order with Multiple Exceptions ............................................................. 92
5.7 Usage Notes ...................................................................................................................... 94
Section 6 Floating-Point Unit (FPU).................................................................97
6.1 Features............................................................................................................................. 97
6.2 Data Formats..................................................................................................................... 98
6.2.1 Floating-Point Format.......................................................................................... 98
6.2.2 Non-Numbers (NaN) ........................................................................................... 101
6.2.3 Denormalized Numbers ....................................................................................... 102
6.3 Register Descriptions........................................................................................................ 103
6.3.1 Floating-Point Registers ...................................................................................... 103
6.3.2 Floating-Point Status/Control Register (FPSCR) ................................................ 105
6.3.3 Floating-Point Communication Register (FPUL) ................................................ 107
6.4 Rounding........................................................................................................................... 108
6.5 Floating-Point Exceptions................................................................................................. 109
6.5.1 General FPU Disable Exceptions and Slot FPU Disable Exceptions .................. 109
6.5.2 FPU Exception Sources ....................................................................................... 109
6.5.3 FPU Exception Handling..................................................................................... 110
6.6 Graphics Support Functions.............................................................................................. 111
6.6.1 Geometric Operation Instructions........................................................................ 111
6.6.2 Pair Single-Precision Data Transfer..................................................................... 112
Section 7 Memory Management Unit (MMU)..................................................113
7.1 Overview of MMU ........................................................................................................... 113
7.1.1 Address Spaces .................................................................................................... 115
7.2 Register Descriptions........................................................................................................ 121
7.2.1 Page Table Entry High Register (PTEH)............................................................. 122
7.2.2 Page Table Entry Low Register (PTEL).............................................................. 123
7.2.3 Translation Table Base Register (TTB)............................................................... 124
7.2.4 TLB Exception Address Register (TEA)............................................................. 124
7.2.5 MMU Control Register (MMUCR)..................................................................... 125
7.2.6 Physical Address Space Control Register (PASCR)............................................ 128
7.2.7 Instruction Re-Fetch Inhibit Control Register (IRMCR) ..................................... 129
7.3 TLB Functions .................................................................................................................. 131
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