Renesas SuperH SH-4A - Page 11

Rev. 1.50, 10/04, page xi of xx
7.3.1 Unified TLB (UTLB) Configuration ................................................................... 131
7.3.2 Instruction TLB (ITLB) Configuration................................................................ 133
7.3.3 Address Translation Method................................................................................ 134
7.4 MMU Functions................................................................................................................ 136
7.4.1 MMU Hardware Management............................................................................. 136
7.4.2 MMU Software Management .............................................................................. 136
7.4.3 MMU Instruction (LDTLB)................................................................................. 137
7.4.4 Hardware ITLB Miss Handling ........................................................................... 139
7.4.5 Avoiding Synonym Problems.............................................................................. 139
7.5 MMU Exceptions.............................................................................................................. 140
7.5.1 Instruction TLB Multiple Hit Exception.............................................................. 140
7.5.2 Instruction TLB Miss Exception.......................................................................... 141
7.5.3 Instruction TLB Protection Violation Exception ................................................. 142
7.5.4 Data TLB Multiple Hit Exception ....................................................................... 143
7.5.5 Data TLB Miss Exception ................................................................................... 143
7.5.6 Data TLB Protection Violation Exception........................................................... 144
7.5.7 Initial Page Write Exception................................................................................ 145
7.6 Memory-Mapped TLB Configuration............................................................................... 146
7.6.1 ITLB Address Array ............................................................................................ 147
7.6.2 ITLB Data Array.................................................................................................. 148
7.6.3 UTLB Address Array........................................................................................... 149
7.6.4 UTLB Data Array ................................................................................................ 150
7.7 32-Bit Address Extended Mode........................................................................................ 151
7.7.1 Overview of 32-Bit Address Extended Mode...................................................... 152
7.7.2 Transition to 32-Bit Address Extended Mode ..................................................... 152
7.7.3 Privileged Space Mapping Buffer (PMB) Configuration .................................... 152
7.7.4 PMB Function...................................................................................................... 154
7.7.5 Memory-Mapped PMB Configuration................................................................. 154
7.7.6 Notes on Using 32-Bit Address Extended Mode ................................................. 156
Section 8 Caches................................................................................................159
8.1 Features............................................................................................................................. 159
8.2 Register Descriptions........................................................................................................ 162
8.2.1 Cache Control Register (CCR) ............................................................................ 163
8.2.2 Queue Address Control Register 0 (QACR0)...................................................... 165
8.2.3 Queue Address Control Register 1 (QACR1)...................................................... 166
8.2.4 On-Chip Memory Control Register (RAMCR) ................................................... 167
8.3 Operand Cache Operation................................................................................................. 169
8.3.1 Read Operation .................................................................................................... 169
8.3.2 Prefetch Operation ............................................................................................... 170
8.3.3 Write Operation ................................................................................................... 171
8.3.4 Write-Back Buffer ............................................................................................... 172
8.3.5 Write-Through Buffer.......................................................................................... 172