Rev. 1.50, 10/04, page xii of xx
8.3.6 OC Two-Way Mode ............................................................................................ 173
8.4 Instruction Cache Operation ............................................................................................. 173
8.4.1 Read Operation .................................................................................................... 173
8.4.2 Prefetch Operation............................................................................................... 174
8.4.3 IC Two-Way Mode.............................................................................................. 174
8.5 Cache Operation Instruction ............................................................................................. 175
8.5.1 Coherency between Cache and External Memory ............................................... 175
8.5.2 Prefetch Operation............................................................................................... 176
8.6 Memory-Mapped Cache Configuration ............................................................................ 176
8.6.1 IC Address Array................................................................................................. 177
8.6.2 IC Data Array ...................................................................................................... 178
8.6.3 OC Address Array ............................................................................................... 179
8.6.4 OC Data Array..................................................................................................... 181
8.7 Store Queues..................................................................................................................... 182
8.7.1 SQ Configuration................................................................................................. 182
8.7.2 Writing to SQ....................................................................................................... 182
8.7.3 Transfer to External Memory .............................................................................. 183
8.7.4 Determination of SQ Access Exception............................................................... 184
8.7.5 Reading from SQ ................................................................................................. 184
8.8 Notes on Using 32-Bit Address Extended Mode .............................................................. 185
Section 9 L Memory.......................................................................................... 187
9.1 Features............................................................................................................................. 187
9.2 Register Descriptions........................................................................................................ 188
9.2.1 On-Chip Memory Control Register (RAMCR) ................................................... 189
9.2.2 L Memory Transfer Source Address Register 0 (LSA0) ..................................... 190
9.2.3 L Memory Transfer Source Address Register 1 (LSA1) ..................................... 191
9.2.4 L Memory Transfer Destination Address Register 0 (LDA0) ............................. 193
9.2.5 L Memory Transfer Destination Address Register 1 (LDA1) ............................. 195
9.3 Operation .......................................................................................................................... 197
9.3.1 Access from the CPU and FPU............................................................................ 197
9.3.2 Access from the SuperHyway Bus Master Module ............................................. 197
9.3.3 Block Transfer ..................................................................................................... 197
9.4 L Memory Protective Functions ....................................................................................... 199
9.5 Usage Notes ...................................................................................................................... 200
9.5.1 Page Conflict ....................................................................................................... 200
9.5.2 L Memory Coherency.......................................................................................... 200
9.5.3 Sleep Mode .......................................................................................................... 200
9.6 Notes on Using 32-Bit Address Extended Mode .............................................................. 200
Section 10 Instruction Descriptions...................................................................201
10.1 CPU instruction.................................................................................................................202
10.1.1 ADD (Add binary): Arithmetic Instruction ......................................................... 204
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