Rev. 1.50, 10/04, page 116 of 448
H'0000 0000
H'8000 0000
H'E000 0000
H'E400 0000
H'E500 0000
H'E600 0000
H'FFFF FFFF
H'0000 0000
H'8000 0000
H'FFFF FFFF
H'A000 0000
H'C000 0000
H'E000 0000
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
Physical
address space
Address error
Address error
Address error
On-chip memory area
Store queue area
User modePrivileged mode
P1 area
Cacheable
P0 area
Cacheable
P2 area
Non-cacheable
P3 area
Cacheable
P4 area
Non-cacheable
U0 area
Cacheable
Figure 7.2 Virtual Address Space (AT in MMUCR= 0)
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
Physical
address space
256
256
U0 area
Cacheable
Address translation possible
Address error
Address error
On-chip memory area
Address error
Store queue area
P0 area
Cacheable
Address translation possible
User mode
Privileged mode
P1 area
Cacheable
Address translation not possible
P2 area
Non-cacheable
Address translation not possible
P3 area
Cacheable
Address translation possible
P4 area
Non-cacheable
Address translation not possible
H'0000 0000
H'8000 0000
H'E000 0000
H'E400 0000
H'E500 0000
H'E600 0000
H'FFFF FFFFH'FFFF FFFF
H'0000 0000
H'8000 0000
H'A000 0000
H'C000 0000
H'E000 0000
Figure 7.3 Virtual Address Space (AT in MMUCR= 1)