Rev. 1.50, 10/04, page 117 of 448
• P0, P3, and U0 Areas:
The P0, P3, and U0 areas allow address translation using the TLB and access using the cache.
When the MMU is disabled, replacing the upper 3 bits of an address with 0s gives the
corresponding physical address. Whether or not the cache is used is determined by the CCR
setting. When the cache is used, switching between the copy-back method and the write-
through method for write accesses is specified by the WT bit in CCR.
When the MMU is enabled, these areas can be mapped onto any physical address space in 1-,
4-, or 64-Kbyte, or 1-Mbyte page units using the TLB. When CCR is in the cache enabled state
and the C bit for the corresponding page of the TLB entry is 1, accesses can be performed
using the cache. When the cache is used, switching between the copy-back method and the
write-through method for write accesses is specified by the WT bit of the TLB entry.
When the P0, P3, and U0 areas are mapped onto the control register area which is allocated in
the area 7 in physical address space by means of the TLB, the C bit for the corresponding page
must be cleared to 0.
• P1 Area:
The P1 area does not allow address translation using the TLB but can be accessed using the
cache.
Regardless of whether the MMU is enabled or disabled, clearing the upper 3 bits of an address
to 0 gives the corresponding physical address. Whether or not the cache is used is determined
by the CCR setting. When the cache is used, switching between the copy-back method and the
write-through method for write accesses is specified by the CB bit in CCR.
• P2 Area:
The P2 area does not allow address translation using the TLB and access using the cache.
Regardless of whether the MMU is enabled or disabled, clearing the upper 3 bits of an address
to 0 gives the corresponding physical address.
• P4 Area:
The P4 area is mapped onto the internal resource of the SH-4A. This area except the store
queue and on-chip memory areas does not allow address translation using the TLB. This area
cannot be accessed using the cache. The P4 area is shown in detail in figure 7.4.
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