Rev. 1.50, 10/04, page 437 of 448
Main Revisions and Additions in this Edition
Item Page Revision (See Manual for Details)
Preface — Deleted.
The SH-4A is a RISC (Reduced Instruction Set
Computer) microcomputer which includes a Renesas
Technology-original RISC CPU as its core. and the
peripheral functions required to configure a system.
1.1 Features 1 Amended.
The SH-4A is a 32-bit RISC (reduced instruction set
computer) microprocessor that is upward compatible
with the SH-1, SH-2, SH-3, SH
-3E, and SH-4
microcomputers at instruction set code level. Its 16-bit
fixed-length instruction set enables program code size
to be reduced by almost 50% compared with 32-bit
instructions.
Table 1.1 Features
CPU
1 Amended.
• RISC-type instruction set (upward compatible with
the SH-1, SH-2, SH-3, and SH-4 microcomputers)
Table 1.1 Features
L memory
3 Amended.
• Two independent read/write ports
8-/16-/32-/64-bit access from the CPU
8-/16-/32-/64-bit and 16-/32-byte access from
the external devices
Note: For the size of L memory, see the hardware
manual of the target product.
Table 1.2 Changes from SH-4 to
SH-4A
4 Amended.
Section No. and
Name
Sub-
section
Sub-section
Name Changes
9 instructions are added as
CPU instructions.
3. Instruction Set 3.3 Instruction Set
3 instructions are added as
FPU instructions.
4. Pipelining 4.2 Parallel-
Executability
9 instructions are added as
CPU instructions.
3 instructions are added as
FPU instructions.
5 Added.
Section No. and
Name
Sub-
section
Sub-section
Name Changes
7. Memory
Management Unit
7.7 32-Bit Address
Extended Mode
Newly added.
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