Rev. 1.50, 10/04, page 214 of 448
10.1.7 BRA (Branch): Branch Instruction
Format Operation Instruction Code Cycle T Bit
BRA label PC + 4 + disp × 2 → PC 1010dddddddddddd 1 —
Description: This is an unconditional branch instruction. The branch destination is address (PC +
4 + displacement × 2). The PC source value is the BRA instruction address. As the 12-bit
displacement is multiplied by two after sign-extension, the branch destination can be located in the
range from –4096 to +4094 bytes from the BRA instruction. If the branch destination cannot be
reached, this branch can be performed with a JMP instruction.
Notes: As this is a delayed branch instruction, the instruction following this instruction is executed
before the branch destination instruction.
Interrupts are not accepted between this instruction and the following instruction. If the following
instruction is a branch instruction, it is identified as a slot illegal instruction.
Operation:
BRA(int d) /* BRA disp */
{
int disp;
unsigned int temp;
temp = PC;
if ((d&0x800)==0)
disp = (0x00000FFF & d);
else disp = (0xFFFFF000 | d);
PC = PC + 4 + (disp<<1);
Delay_Slot(temp+2);
}
Example:
BRA TRGET ;Branch to TRGET.
ADD R0,R1 ;ADD executed before branch.
NOP ;
TRGET: ;← BRA instruction branch destination
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