Renesas SuperH SH-4A - DMULU.L (Double-Length Multiply as Unsigned): Arithmetic Instruction

Rev. 1.50, 10/04, page 237 of 448
10.1.19 DMULU.L (Double-length Multiply as Unsigned): Arithmetic Instruction
Format Operation Instruction Code Cycle T Bit
DMULU.L Rm,Rn Unsigned,
Rn × Rm →MAC
0011nnnnmmmm0101 2 —
Description: This instruction performs 32-bit multiplication of the contents of general register Rn
by the contents of Rm, and stores the 64-bit result in the MACH and MACL registers. The
multiplication is performed as an unsigned arithmetic operation.
Notes: None
Operation:
DMULU(long m, long n) /* DMULU.L Rm,Rn */
{
unsigned long RnL,RnH,RmL,RmH,Res0,Res1,Res2;
unsigned long temp0,temp1,temp2,temp3;
RnL = R[n] & 0x0000FFFF;
RnH = (R[n]>>16) & 0x0000FFFF;
RmL = R[m] & 0x0000FFFF;
RmH = (R[m]>>16) & 0x0000FFFF;
temp0 = RmL*RnL;
temp1 = RmH*RnL;
temp2 = RmL*RnH;
temp3 = RmH*RnH;
Res2 = 0
Res1 = temp1 + temp2;
if (Res1<temp1) Res2 += 0x00010000;
temp1 = (Res1<<16) & 0xFFFF0000;
Res0 = temp0 + temp1;
if (Res0<temp0) Res2++;