Rev. 1.50, 10/04, page 366 of 448
10.3.2 FADD (Floating-point ADD): Floating-Point Instruction
PR Format Operation Instruction Code Cycle T Bit
0 FADD FRm,FRn FRn+FRm → FRn 1111nnnnmmmm0000 1 —
1 FADD DRm,DRn DRn+DRm → DRn 1111nnn0mmm00000 1 —
Description: When FPSCR.PR = 0: Arithmetically adds the two single-precision floating-point
numbers in FRn and FRm, and stores the result in FRn.
When FPSCR.PR = 1: Arithmetically adds the two double-precision floating-point numbers in
DRn and DRm, and stores the result in DRn.
When FPSCR.enable.I is set, an FPU exception trap is generated regardless of whether or not an
exception has occurred. When FPSCR.enable.O/U is set, FPU exception traps are generated on
actual generation by the FPU exception source and on the satisfaction of certain special conditions
that apply to this the instruction. These special conditions are described in the remaining parts of
this section. When an exception occurs, correct exception information is reflected in FPSCR.cause
and FPSCR.flag, and FRn or DRn is not updated. Appropriate processing should therefore be
performed by software.
Notes: None
Operation:
void FADD (int m,n)
{
pc += 2;
clear_cause();
if((data_type_of(m) == sNaN) ||
(data_type_of(n) == sNaN)) invalid(n);
else if((data_type_of(m) == qNaN) ||
(data_type_of(n) == qNaN)) qnan(n);
else if((data_type_of(m) == DENORM) ||
(data_type_of(n) == DENORM)) set_E();
else switch (data_type_of(m)){
case NORM: switch (data_type_of(n)){
case NORM: normal_faddsub(m,n,ADD); break;
case PZERO:
case NZERO:register_copy(m,n); break;
default: break;
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