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Renesas SuperH SH-4A User Manual

Renesas SuperH SH-4A
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Rev. 1.50, 10/04, page 291 of 448
10.1.48 OCBP (Operand Cache Block Purge): Data Transfer Instruction
Format Operation Instruction Code Cycle T Bit
OCBP @Rn Writes back and invalidates
operand cache block
0000nnnn10100011 1 —
Description: This instruction accesses data using the contents indicated by effective address Rn.
If the cache is hit and there is unwritten information (U bit = 1), the corresponding cache block is
written back to external memory and that block is invalidated (the V bit is cleared to 0). If there is
no unwritten information (U bit = 0), the block is simply invalidated. No operation is performed in
the case of a cache miss or an access to a non-cache area.
Notes: None
Operation:
OCBP(int n) /* OCBP @Rn */
{
if(is_dirty_block(R[n])) write_back(R[n])
invalidate_operand_cache_block(R[n]);
PC += 2;
}
Possible Exceptions:
• Data TLB multiple-hit exception
• Data TLB miss exception
• Data TLB protection violation exception
• Data address error
Note that the above exceptions are generated even if OCBP does not operate.

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Renesas SuperH SH-4A Specifications

General IconGeneral
BrandRenesas
ModelSuperH SH-4A
CategoryComputer Hardware
LanguageEnglish

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