Renesas SuperH SH-4A - TST (Test Logical): Logical Instruction

Rev. 1.50, 10/04, page 337 of 448
10.1.79 TST (Test Logical): Logical Instruction
Format Operation Instruction Code Cycle T Bit
TST Rm,Rn Rn & Rm; if result is 0,
1 → T, else 0 → T
0010nnnnmmmm1000 1 Test result
TST #imm,R0 R0 & imm; if result is 0,
1 → T, else 0 → T
11001000iiiiiiii 1 Test result
TST.B #imm,@(R0,GBR) (R0 + GBR) & imm;
if result is 0, 1 → T,
else 0 → T
11001100iiiiiiii 3 Test result
Description: This instruction ANDs the contents of general registers Rn and Rm, and sets the T
bit if the result is zero. If the result is nonzero, the T bit is cleared. The contents of Rn are not
changed.
This instruction can be used to AND general register R0 contents with zero-extended 8-bit
immediate data, or, in indexed GBR indirect addressing mode, to AND 8-bit memory with 8-bit
immediate data. The contents of R0 or the memory are not changed.
Notes: None
Operation:
TST(long m, long n) /* TST Rm,Rn */
{
if ((R[n]&R[m])==0) T = 1;
else T = 0;
PC += 2;
}
TSTI(long i) /* TST #imm,R0 */
{
long temp;
temp = R[0]&(0x000000FF & (long)i);
if (temp==0) T = 1;
else T = 0;
PC += 2;
}