Renesas SuperH SH-4A User Manual

Rev. 1.50, 10/04, page 430 of 448
11.2 Register States in Each Operating Mode
Module Name Abbreviation
Power-on
Reset
Manual
Reset Sleep Standby
Exception
handling
TRAPA exception register TRA Undefined Undefined Retained Retained
Exception event register EXPEVT H'0000 0000 H'0000 0020 Retained Retained
Interrupt event register INTEVT Undefined Undefined Retained Retained
MMU Page table entry high
register
PTEH Undefined Undefined Retained Retained
Page table entry low
register
PTEL Undefined Undefined Retained Retained
Translation table base
register
TTB Undefined Undefined Retained Retained
TLB exception address
register
TEA Undefined Retained Retained Retained
MMU control register MMUCR H'0000 0000 H'0000 0000 Retained Retained
Physical address space
control register
PASCR H'0000 0000 H'0000 0000 Retained Retained
Instruction re-fetch inhibit
control register
IRMCR H'0000 0000 H'0000 0000 Retained Retained
Cache Cache control register CCR H'0000 0000 H'0000 0000 Retained Retained
Queue address control
register 0
QACR0 Undefined Undefined Retained Retained
Queue address control
register 1
QACR1 Undefined Undefined Retained Retained
On-chip memory control
register
RAMCR H'0000 0000 H'0000 0000 Retained Retained
L memory L memory transfer source
address register 0
LSA0 Undefined Undefined Retained Retained
L memory transfer source
address register 1
LSA1 Undefined Undefined Retained Retained
L memory transfer
destination address
register 0
LDA0 Undefined Undefined Retained Retained
L memory transfer
destination address
register 1
LDA1 Undefined Undefined Retained Retained

Renesas SuperH SH-4A Specifications

General

Brand	Renesas
Model	SuperH SH-4A
Category	Computer Hardware
Language	English