Rev. 1.50, 10/04, page 23 of 448
Section 3 Instruction Set
The SH-4A's instruction set is implemented with 16-bit fixed-length instructions. The SH-4A can
use byte (8-bit), word (16-bit), longword (32-bit), and quadword (64-bit) data sizes for memory
access. Single-precision floating-point data (32 bits) can be moved to and from memory using
longword or quadword size. Double-precision floating-point data (64 bits) can be moved to and
from memory using longword size. When the SH-4A moves byte-size or word-size data from
memory to a register, the data is sign-extended.
3.1 Execution Environment
PC: At the start of instruction execution, the PC indicates the address of the instruction itself.
Load-Store Architecture: The SH-4A has a load-store architecture in which operations are
basically executed using registers. Except for bit-manipulation operations such as logical AND
that are executed directly in memory, operands in an operation that requires memory access are
loaded into registers and the operation is executed between the registers.
Delayed Branches: Except for the two branch instructions BF and BT, the SH-4A's branch
instructions and RTE are delayed branches. In a delayed branch, the instruction following the
branch is executed before the branch destination instruction.
Delay Slot: This execution slot following a delayed branch is called a delay slot. For example, the
BRA execution sequence is as follows:
Table 3.1 Execution Order of Delayed Branch Instructions
Instructions Execution Order
BRA TARGET (Delayed branch instruction) BRA
ADD (Delay slot) ↓
: ADD
: ↓
TARGET target-inst (Branch destination instruction) target-inst
A slot illegal instruction exception may occur when a specific instruction is executed in a delay
slot. For details, see section 5, Exception Handling. The instruction following BF/S or BT/S for
which the branch is not taken is also a delay slot instruction.
T Bit: The T bit in SR is used to show the result of a compare operation, and is referenced by a
conditional branch instruction. An example of the use of a conditional branch instruction is shown
below.
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