Renesas SuperH SH-4A

Rev. 1.50, 10/04, page 378 of 448
10.3.6 FDIV (Floating-point Divide): Floating-Point Instruction
PR Format Operation Instruction Code Cycle T Bit
0 FDIV FRm,FRn FRn/FRm → FRn 1111nnnnmmmm0011 14 —
1 FDIV DRm,DRn DRn/DRm → DRn 1111nnn0mmm00011 30 —
Description: When FPSCR.PR = 0: Arithmetically divides the single-precision floating-point
number in FRn by the single-precision floating-point number in FRm, and stores the result in FRn.
When FPSCR.PR = 1: Arithmetically divides the double-precision floating-point number in DRn
by the double-precision floating-point number in DRm, and stores the result in DRn.
When FPSCR.enable.I is set, an FPU exception trap is generated regardless of whether or not an
exception has occurred. When FPSCR.enable.O/U is set, FPU exception traps are generated on
actual generation by the FPU exception source and on the satisfaction of certain special conditions
that apply to this the instruction. These special conditions are described in the remaining parts of
this section. When an exception occurs, correct exception information is reflected in FPSCR.cause
and FPSCR.flag, and FRn or DRn is not updated. Appropriate processing should therefore be
performed by software.
Notes: None
Operation:
void FDIV(int m,n) /* FDIV FRm,FRn */
{
pc += 2;
clear_cause();
if((data_type_of(m) == sNaN) ||
(data_type_of(n) == sNaN)) invalid(n);
else if((data_type_of(m) == qNaN) ||
(data_type_of(n) == qNaN)) qnan(n);
else switch (data_type_of(m)){
case NORM: switch (data_type_of(n)){
case PINF:
case NINF: inf(n,sign_of(m)^sign_of(n));break;
case PZERO:
case NZERO: zero(n,sign_of(m)^sign_of(n));break;
case DENORM:set_E(); break;
default: normal_fdiv(m,n); break;