Renesas SuperH SH-4A

Rev. 1.50, 10/04, page 245 of 448
10.1.25 LDC (Load to Control Register): System Control Instruction
Format Operation Instruction Code Cycle T Bit
LDC Rm, GBR
Rm → GBR
0100mmmm00011110
1 —
LDC Rm, VBR
Rm → VBR
0100mmmm00101110
1 —
LDC Rm, SGR
Rm → SGR
0100mmmm00111010
4 —
LDC Rm, SSR
Rm → SSR
0100mmmm00111110
1 —
LDC Rm, SPC
Rm → SPC
0100mmmm01001110
1
LDC Rm, DBR
Rm → DBR
0100mmmm11111010
4 —
LDC Rm, R0_BANK
Rm → R0_BANK
0100mmmm10001110
1 —
LDC Rm, R1_BANK
Rm → R1_BANK
0100mmmm10011110
1 —
LDC Rm, R2_BANK
Rm → R2_BANK
0100mmmm10101110
1 —
LDC Rm, R3_BANK
Rm → R3_BANK
0100mmmm10111110
1 —
LDC Rm, R4_BANK
Rm → R4_BANK
0100mmmm11001110
1 —
LDC Rm, R5_BANK
Rm → R5_BANK
0100mmmm11011110
1 —
LDC Rm, R6_BANK
Rm → R6_BANK
0100mmmm11101110
1 —
LDC Rm, R7_BANK
Rm → R7_BANK
0100mmmm11111110
1 —
LDC.L @Rm+, GBR
(Rm) → GBR, Rm+4 → Rm
0100mmmm00010111
1 —
LDC.L @Rm+, VBR
(Rm) → VBR, Rm+4 → Rm
0100mmmm00100111
1 —
LDC.L @Rm+, SGR
(Rm) → SGR, Rm+4 → Rm
0100mmmm00110110
4 —
LDC.L @Rm+, SSR
(Rm) → SSR, Rm+4 → Rm
0100mmmm00110111
1 —
LDC.L @Rm+, SPC
(Rm) → SPC, Rm+4 → Rm
0100mmmm01000111
1 —
LDC.L @Rm+, DBR
(Rm) → DBR, Rm+4 → Rm
0100mmmm11110110
4 —
LDC.L @Rm+, R0_BANK
(Rm) → R0_BANK, Rm+4 → Rm
0100mmmm10000111
1 —
LDC.L @Rm+, R1_BANK
(Rm) → R1_BANK, Rm+4 → Rm
0100mmmm10010111
1 —
LDC.L @Rm+, R2_BANK
(Rm) → R2_BANK, Rm+4 → Rm
0100mmmm10100111
1 —
LDC.L @Rm+, R3_BANK
(Rm) → R3_BANK, Rm+4 → Rm
0100mmmm10110111
1 —
LDC.L @Rm+, R4_BANK
(Rm) → R4_BANK, Rm+4 → Rm
0100mmmm11000111
1 —
LDC.L @Rm+, R5_BANK
(Rm) → R5_BANK, Rm+4 → Rm
0100mmmm11010111
1 —
LDC.L @Rm+, R6_BANK
(Rm) → R6_BANK, Rm+4 → Rm
0100mmmm11100111
1 —
LDC.L @Rm+, R7_BANK
(Rm) → R7_BANK, Rm+4 → Rm
0100mmmm11110111
1 —
Description: These instructions store the source operand in the control register GBR, VBR, SSR,
SPC, DBR, SGR, or R0_BANK to R7_BANK.