Renesas SuperH SH-4A - FRCHG (FR-Bit Change): Floating-Point Instruction

Rev. 1.50, 10/04, page 407 of 448
10.3.18 FRCHG (FR-bit Change): Floating-Point Instruction
PR Format Operation Instruction Code Cycle T Bit
0 FRCHG ~FPSCR.FR → FPSCR.FR 1111101111111101 1 —
1 — — — — —
Description: This instruction inverts the FR bit in floating-point register FPSCR. When the FR bit
in FPSCR is changed, FR0 to FR15 in FPR0_BANK0 to FPR15_BANK0 and FPR0_BANK1 to
FPR15_BANK1 become XR0 to XR15, and XR0 to XR15 become FR0 to FR15. When
FPSCR.FR = 0, FPR0_BANK0 to FPR15_BANK0 correspond to FR0 to FR15, and
FPR0_BANK1 to FPR15_BANK1 correspond to XR0 to XR15. When FPSCR.FR = 1,
FPR0_BANK1 to FPR15_BANK1 correspond to FR0 to FR15, and FPR0_BANK0 to
FPR15_BANK0 correspond to XR0 to XR15.
Notes: None
Operation:
void FRCHG() /* FRCHG */
{
if(FPSCR_PR == 0){
FPSCR ^= 0x00200000; /* bit 21 */
PC += 2;
}
else undefined_operation();
}
Possible Exceptions: None