Renesas SuperH SH-4A User Manual

Rev. 1.50, 10/04, page 286 of 448
10.1.43 NEG (Negate): Arithmetic Instruction
Format Operation Instruction Code Cycle T Bit
NEG Rm,Rn 0 - Rm → Rn 0110nnnnmmmm1011 1 —
Description: This instruction finds the two's complement of the contents of general register Rm
and stores the result in Rn. That is, it subtracts Rm from 0 and stores the result in Rn.
Notes: None
Operation:
NEG(long m, long n) /* NEG Rm,Rn */
{
R[n] = 0-R[m];
PC += 2;
}
Example:
NEG R0,R1 ;Before execution R0 = H'00000001
;After execution R1 = H'FFFFFFFF

Renesas SuperH SH-4A Specifications

General

Architecture	32-bit RISC
Core	SH-4A
Data Bus Width	32-bit
Instruction Set	SuperH
Cache	32 KB instruction, 32 KB data
Number of Registers	16 general-purpose, 16 control
MMU	Yes
Typical Applications	Embedded systems, automotive, consumer electronics
Manufacturing Process	90 nm
Voltage	1.2V core, 3.3V I/O
FPU	Yes
Package	BGA