Renesas SuperH SH-4A

Rev. 1.50, 10/04, page 373 of 448
10.3.4 FCNVDS (Floating-point Convert Double to Single Precision): Floating-Point
Instruction
PR Format Operation Instruction Code Cycle T Bit
0 — — — — —
1 FCNVDS DRm,FPUL (float)DRm → FPUL 1111mmm010111101 1 —
Description: When FPSCR.PR = 1: This instruction converts the double-precision floating-point
number in DRm to a single-precision floating-point number, and stores the result in FPUL.
When FPSCR.enable. I is set, an FPU exception trap is generated regardless of whether or not an
exception has occurred. When FPSCR.enable.O/U is set, FPU exception traps are generated on
actual generation by the FPU exception source and on the satisfaction of certain special conditions
that apply to this the instruction. These special conditions are described in the remaining parts of
this section. When an exception occurs, correct exception information is reflected in FPSCR.cause
and FPSCR.flag, and FPUL is not updated. Appropriate processing should therefore be performed
by software.
Notes: None
Operation:
void FCNVDS(int m, float *FPUL){
case((FPSCR.PR){
0: undefined_operation(); /* reserved */
1: fcnvds(m, *FPUL); break; /* FCNVDS */
}
}
void fcnvds(int m, float *FPUL)
{
pc += 2;
clear_cause();
case(data_type_of(m)){
NORM :
PZERO :
NZERO : normal_ fcnvds(m, *FPUL); break;
DENORM : set_E();
PINF : *FPUL = 0x7f800000; break;
NINF : *FPUL = 0xff800000; break;