Rev. 1.50, 10/04, page 349 of 448
10.2.5 LDS (Load to FPU System register): System Control Instruction
Format Operation Instruction Code Cycle T Bit
LDS Rm,FPUL Rm → FPUL 0100mmmm01011010 1 —
LDS.L @Rm+,FPUL (Rm) → FPUL, Rm + 4
→ Rm
0100mmmm01010110 1 —
LDS Rm,FPSCR Rm → FPSCR 0100mmmm01101010 1 —
LDS.L @Rm+,FPSCR (Rm) → FPSCR, Rm + 4
→ Rm
0100mmmm01100110 1 —
Description: This instruction loads the source operand into FPU system registers FPUL and
FPSCR.
Notes: None
Operation:
#define FPSCR_MASK 0x003FFFFF
LDSFPUL(int m, int *FPUL) /* LDS Rm,FPUL */
{
*FPUL = R[m];
PC += 2;
}
LDSMFPUL(int m, int *FPUL) /* LDS.L @Rm+,FPUL */
{
*FPUL = Read_Long(R[m]);
R[m] += 4;
PC += 2;
}
LDSFPSCR(int m) /* LDS Rm,FPSCR */
{
FPSCR = R[m] & FPSCR_MASK;
PC += 2;
}
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