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Renesas SuperH SH-4A User Manual

Renesas SuperH SH-4A
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Rev. 1.50, 10/04, page 317 of 448
10.1.67 SHLR (Shift Logical Right): Shift Instruction
Format Operation Instruction Code Cycle T Bit
SHLR Rn 0 → Rn → T 0100nnnn00000001 1 LSB
Description: This instruction logically shifts the contents of general register Rn one bit to the
right, and stores the result in Rn. The bit shifted out of the operand is transferred to the T bit.
MSB LSB
SHLR
T0
Notes: None
Operation:
SHLR(long n) /* SHLR Rn */
{
if ((R[n] & 0x00000001)==0) T = 0;
else T = 1;
R[n] >>= 1;
R[n] &= 0x7FFFFFFF;
PC += 2;
}
Example:
SHLR R0 ;Before execution R0 = H'80000001, T = 0
;After execution R0 = H'40000000, T = 1

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Renesas SuperH SH-4A Specifications

General IconGeneral
BrandRenesas
ModelSuperH SH-4A
CategoryComputer Hardware
LanguageEnglish

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