Renesas SuperH SH-4A - Register Addresses; (By Functional Module, in Order of the Corresponding Section Numbers)

Rev. 1.50, 10/04, page 428 of 448
11.1 Register Addresses
(by functional module, in order of the corresponding section
numbers)
Entries under Access size indicates numbers of bits.
Note: Access to undefined or reserved addresses is prohibited. Since operation or continued
operation is not guaranteed when these registers are accessed, do not attempt such access.
Module Name Abbreviation R/W P4 Address*
Area 7
Address*
Access
Size
Exception
handling
TRAPA exception register TRA R/W H'FF00 0020 H'1F00 0020 32
Exception event register EXPEVT R/W H'FF00 0024 H'1F00 0024 32
Interrupt event register INTEVT R/W H'FF00 0028 H'1F00 0028 32
MMU Page table entry high
register
PTEH R/W H'FF00 0000 H'1F00 0000 32
Page table entry low
register
PTEL R/W H'FF00 0004 H'1F00 0004 32
Translation table base
register
TTB R/W H'FF00 0008 H'1F00 0008 32
TLB exception address
register
TEA R/W H'FF00 000C H'1F00 000C 32
MMU control register MMUCR R/W H'FF00 0010 H'1F00 0010 32
Physical address space
control register
PASCR R/W H'FF00 0070 H'1F00 0070 32
Instruction re-fetch inhibit
control register
IRMCR R/W H'FF00 0078 H'1F00 0078 32
Cache Cache control register CCR R/W H'FF00 001C H'1F00 001C 32
Queue address control
register 0
QACR0 R/W H'FF00 0038 H'1F00 0038 32
Queue address control
register 1
QACR1 R/W H'FF00 003C H'1F00 003C 32
On-chip memory control
register
RAMCR R/W H'FF00 0074 H'1F00 0074 32