Renesas SuperH SH-4A - Changes from SH-4 to SH-4 A

Rev. 1.50, 10/04, page 4 of 448
1.2 Changes from SH-4 to SH-4A
Table 1.2 summarizes the changes from SH-4 to SH-4A based on the sections and sub-sections in
this manual.
Table 1.2 Changes from SH-4 to SH-4A
Section No. and
Name
Sub-
section
Sub-section
Name Changes
1. Overview   Modified entirely
(Detailed differences are described in the
following sections).
2. Programming
Model
2.2 Register
Descriptions
The operations in SZ=1 and PR=1 are
added to the floating point status/control
register (FPSCR).
9 instructions are added as CPU
instructions.
3. Instruction Set 3.3 Instruction Set
3 instructions are added as FPU
instructions.
4.1 Pipelines The number of stages in the pipeline is
changed from five to seven.
9 instructions are added as CPU
instructions.
3 instructions are added as FPU
instructions.
4.2 Parallel-
Executability
Instruction group and parallel execution
combinations are modified.
4. Pipelining
4.3 Execution Cycles The number of execution cycles is
modified.
5. Exception Handling   
6.3.2 Floating-Point
Status/Control
Register (FPSCR)
Operations in SZ = 1 and PR = 1 and each
endian are added
6. FPU
6.5 Floating-Point
Exceptions
Specification of FPU exception detection
condition with FPU exception enabled is
changed.