Renesas SuperH SH-4A User Manual

Rev. 1.50, 10/04, page 5 of 448
Section No. and
Name
Sub-
section
Sub-section
Name Changes
Area P4 configuration is modified.
7.1.1 Address Spaces
On-chip RAM space is deleted.
The page table entry assist register (PTEA)
is deleted.
7.2 Register
Descriptions
A physical address space control register is
added.
7.2.6 Physical Address
Space Control
Register (PASCR)
Newly added
7.2.7 Instruction Re-
Fetch Inhibit
Control Register
(IRMCR)
Newly added.
7.3 TLB Functions Space attribute bits (SA [2:0]) and timing
control bit (TC) are deleted from the TLB.
7.4.5 Avoiding Synonym
Problems
The corresponding bits are modified
according to the cache size change and the
index mode deletion.
7.5.1,
7.5.4
Instruction TLB
Multiple Hit
Exception and
Data TLB Multiple
Hit Exception
Multiple hits during the UTLB search
caused by ITLB mishandling are changed
to be handled as a TLB multiple hit
instruction exception.
7.6 Memory-Mapped
TLB Configuration
Data array 2 in the ITLB and UTLB is
deleted.
Associative writes to the UTLB address
array are changed to not generate data
TLB multiple hit exceptions.
7.6.3 UTLB Address
Array
Memory allocated addresses are changed
from H'F6000000–H'F6FFFFFF to
H'F6000000–H'F60FFFFF.
7. Memory
Management Unit
7.6.4 UTLB Data Array Memory allocated addresses are changed
from H'F7000000–H'F77FFFFF to
H'F7000000–H'F70FFFFF.
7.7 32-Bit Address
Extended Mode
Newly added.

Renesas SuperH SH-4A Specifications

General

Brand	Renesas
Model	SuperH SH-4A
Category	Computer Hardware
Language	English