Renesas SuperH SH-4A - Page 26

Rev. 1.50, 10/04, page 6 of 448
Section No. and
Name
Sub-
section
Sub-section
Name Changes
Instruction cache capacity is changed to 32
Kbytes.
8.1 Features
The caching method is changed to a 4-way
set-associative method.
8.2 Register
Descriptions
An on-chip memory control register is
added.
8.2.1 Cache Control
Register (CCR)
Modified.
(Descriptions in CCR are modified.)
8.2.4 On-Chip Memory
Control Register
(RAMCR)
Newly added.
8.3 Operand Cache
Operation
RAM mode and OC index mode are
deleted.
8.3.6 OC Two-Way
Mode
Newly added.
8.4 Instruction Cache
Operation
IC index mode is deleted.
8.4.3 IC Two-Way Mode Newly added.
8.5.1 Coherency
between Cache
and External
Memory
The ICBI, PREFI, and SYNCO instructions
are added.
8. Caches
8.6 Memory-Mapped
Cache
Configuration
The entry bits and the way bits are modified
according to the size modification and
changed into 4-way set associative cache.
8.8 Notes on Using
32-Bit Address
Extended Mode
Newly added.
9. L Memory   Newly added.
9 instructions are added as CPU
instructions.
10. Instruction
Descriptions
 
3 instructions are added as FPU
instructions.