Rev. 1.50, 10/04, page 216 of 448
10.1.8 BRAF (Branch Far): Branch Instruction (Delayed Branch Instruction)
Format Operation Instruction Code Cycle T Bit
BRAF Rn PC + 4 + Rn → PC 0000nnnn00100011 1 —
Description: This is an unconditional branch instruction. The branch destination is address (PC +
4 + Rn). The branch destination address is the result of adding 4 plus the 32-bit contents of general
register Rn to PC.
Notes: As this is a delayed branch instruction, the instruction following this instruction is executed
before the branch destination instruction.
Interrupts are not accepted between this instruction and the following instruction. If the following
instruction is a branch instruction, it is identified as a slot illegal instruction.
Operation:
BRAF(int n) /* BRAF Rn */
{
unsigned int temp;
temp = PC;
PC = PC + 4 + R[n];
Delay_Slot(temp+2);
}
Example:
MOV.L #(TRGET-BRAF_PC),R0 ;Set displacement.
BRAF R0 ;Branch to TRGET.
ADD R0,R1 ;ADD executed before branch.
BRAF_PC: ;
NOP
TRGET: ;← BRAF instruction branch destination
Possible Exceptions:
• Slot illegal instruction exception
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