Renesas SuperH SH-4A - ADDV (Add with (V Flag) Overflow Check): Arithmetic Instruction

Rev. 1.50, 10/04, page 206 of 448
10.1.3 ADDV (Add with (V flag) Overflow Check): Arithmetic Instruction
Format Operation Instruction Code Cycle T Bit
ADDV Rm,Rn Rn + Rm → Rn,
overflow → T
0011nnnnmmmm1111 1 Overflow
Description: This instruction adds together the contents of general registers Rn and Rm and stores
the result in Rn. If overflow occurs, the T bit is set.
Notes: None
Operation:
ADDV(long m, long n) /* ADDV Rm,Rn */
{
long dest,src,ans;
if ((long)R[n]>=0) dest = 0;
else dest = 1;
if ((long)R[m]>=0) src = 0;
else src = 1;
src += dest;
R[n] += R[m];
if ((long)R[n]>=0) ans = 0;
else ans = 1;
ans += dest;
if (src==0 || src==2) {
if (ans==1) T = 1;
else T = 0;
}
else T = 0;
PC += 2;
}