Rev. 1.50, 10/04, page 389 of 448
10.3.12 FMAC (Floating-point Multiply and Accumulate): Floating-Point Instruction
PR Format Operation Instruction Code Cycle T Bit
0 FMAC FR0,FRm,FRn FR0 × FRm+FRn → FRn 1111nnnnmmmm1110 1 —
1 — — — — —
Description: When FPSCR.PR = 0: This instruction arithmetically multiplies the two single-
precision floating-point numbers in FR0 and FRm, arithmetically adds the contents of FRn, and
stores the result in FRn.
When FPSCR.enable.I is set, an FPU exception trap is generated regardless of whether or not an
exception has occurred. When FPSCR.enable.O/U is set, FPU exception traps are generated on
actual generation by the FPU exception source and on the satisfaction of certain special conditions
that apply to this the instruction. These special conditions are described in the remaining parts of
this section. When an exception occurs, correct exception information is reflected in FPSCR.cause
and FPSCR.flag, and FRn is not updated. Appropriate processing should therefore be performed
by software.
Notes: None
Operation:
void FMAC(int m,n)
{
pc += 2;
clear_cause();
if(FPSCR_PR == 1) undefined_operation();
else if((data_type_of(0) == sNaN) ||
(data_type_of(m) == sNaN) ||
(data_type_of(n) == sNaN)) invalid(n);
else if((data_type_of(0) == qNaN) ||
(data_type_of(m) == qNaN)) qnan(n);
else if((data_type_of(0) == DENORM) ||
(data_type_of(m) == DENORM)) set_E();
else switch (data_type_of(0){
case NORM: switch (data_type_of(m)){
case PZERO:
case NZERO: switch (data_type_of(n)){
case DENORM: set_E(); break;
case qNaN: qnan(n); break;
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