Rev. 1.50, 10/04, page 17 of 448
Floating-Point Status/Control Register (FPSCR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0000000000000100
RRRRRRRRRRR/WR/WR/WR/WR/W
R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
0000000000000001
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Enable (EN)
FR SZ PR DN
Flag RM
Cause
Cause
BIt:
Initial value:
R/W:
BIt:
Initial value:
R/W:
Bit Bit Name
Initial
Value R/W Description
31 to 22 — All 0 R Reserved
For details on reading/writing this bit, see General
Precautions on Handling of Product.
21 FR 0 R/W Floating-Point Register Bank
0: FPR0_BANK0 to FPR15_BANK0 are assigned to
FR0 to FR15 and FPR0_BANK1 to FPR15_BANK1
are assigned to XF0 to XF15
1: FPR0_BANK0 to FPR15_BANK0 are assigned to
XF0 to XF15 and FPR0_BANK1 to FPR15_BANK1
are assigned to FR0 to FR15
20 SZ 0 R/W Transfer Size Mode
0: Data size of FMOV instruction is 32-bits
1: Data size of FMOV instruction is a 32-bit register
pair (64 bits)
For relationship between the SZ bit, PR bit, and endian,
see figure 2.5.
19 PR 0 R/W Precision Mode
0: Floating-point instructions are executed as
single-precision operations
1: Floating-point instructions are executed as
double-precision operations (graphics support
instructions are undefined)
For relationship between the SZ bit, PR bit, and endian,
see figure 2.5
18 DN 1 R/W Denormalization Mode
0: Denormalized number is treated as such
1: Denormalized number is treated as zero
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