Rev. 1.50, 10/04, page 2 of 448
Item Features
Floatingpoint unit
(FPU)
• On-chip floating-point coprocessor
• Supports single-precision (32 bits) and double-precision (64 bits)
• Supports IEEE754-compliant data types and exceptions
• Two rounding modes: Round to Nearest and Round to Zero
• Handling of denormalized numbers: Truncation to zero or interrupt
generation for IEEE754 compliance
• Floating-point registers: 32 bits × 16 words × 2 banks
(single-precision × 16 words or double-precision × 8 words) × 2 banks
• 32-bit CPU-FPU floating-point communication register (FPUL)
• Supports FMAC (multiply-and-accumulate) instruction
• Supports FDIV (divide) and FSQRT (square root) instructions
• Supports FLDI0/FLDI1 (load constant 0/1) instructions
• Instruction execution times
Latency (FADD/FSUB): 3 cycles (single-precision), 5 cycles (double-
precision)
Latency (FMAC/ FMUL): 5 cycles (single-precision), 7 cycles (double-
precision)
Pitch (FADD/FSUB): 1 cycle (single-precision/double-precision)
Pitch (FMAC/FMUL): 1 cycle (single-precision), 3 cycles (double-
precision)
Note: FMAC is supported for single-precision only.
• 3-D graphics instructions (single-precision only):
4-dimensional vector conversion and matrix operations (FTRV): 4 cycles
(pitch), 8 cycles (latency)
4-dimensional vector (FIPR) inner product: 1 cycle (pitch), 5 cycles
(latency)
• Ten-stage pipeline
Memory
management
unit (MMU)
• 4 Gbytes of physical address space, 256 address space identifiers (address
space identifier ASID: 8 bits)
• Supports single virtual memory mode and multiple virtual memory mode
• Supports multiple page sizes: 1 Kbyte, 4 Kbytes, 64 Kbytes, or 1 Mbyte
• 4-entry full associative TLB for instructions
• 64-entry full associative TLB for instructions and operands
• Supports software selection of replacement method and random-counter
replacement algorithms
• Contents of TLB are directly accessible through address mapping
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