Rev. 1.50, 10/04, page 439 of 448
Item Page Revision (See Manual for Details)
Figure 4.2 Instruction Execution
Patterns (7)
51 Amended.
(6-3) LDS.L to FPUL: 1 issue cycle
(6-5) LDS to FPSCR: 1 issue cycle
(6-7) LDS.L to FPSCR: 1 issue cycle
Table 4.2 Instruction Groups 54 Amended.
Instruction
Group Instruction
LS MOV.[BWL] @adr,R
MOV.[BWL] R,@adr
MOVA
MOVCA.L
MOVUA
OCBI
OCBP
OCBWB
PREF
STC CR2,Rn
STC.L CR2,@-Rn
STS SR2,Rn
STS.L SR2,@-Rn
STS SR1,Rn
STS.L SR1,@-Rn
6.5.3 FPU Exception Handling 110 Amended.
• Division by zero (Z): FPSCR.Enable.Z = 1 and
division with a zero divisor or the input of FSRRA is
zero
Figure 7.4 P4 Area 118 Amended.
Operand cache data array
Unified TLB and PMB address array
Unified TLB and PMB data array
H'F800 0000
H'F700 0000
H'F600 0000
7.1.1 Address Spaces
• P4 Area
119 Added.
The area from H'F610 0000 to H'F61F FFFF is used for
direct access to the PMB address array. For details,
see section 7.7.5, Memory-Mapped PMB Configuration.
The area from H'F700 0000 to H'F70F FFFF is used for
direct access to unified TLB data array. For details, see
section 7.6.4, UTLB Data Array.
The area from H'F710 0000 to H'F71F FFFF is used for
direct access to the PMB data array. For details, see
section 7.7.5, Memory-Mapped PMB Configuration.
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