Renesas SuperH SH-4A User Manual

Rev. 1.50, 10/04, page 130 of 448
Bit Bit Name
Initial
Value R/W Description
2 LT 0 R/W Re-Fetch Inhibit after LDTLB Execution
This bit controls whether re-fetch is performed for the
next instruction after the LDTLB instruction has been
executed.
0: Re-fetch is performed
1: Re-fetch is not performed
1 MT 0 R/W Re-Fetch Inhibit after Writing Memory-Mapped TLB
This bit controls whether re-fetch is performed for the
next instruction after writing memory-mapped
ITLB/UTLB while the AT bit in MMUCR is set to 1.
0: Re-fetch is performed
1: Re-fetch is not performed
0 MC 0 R/W Re-Fetch Inhibit after Writing Memory-Mapped IC
This bit controls whether re-fetch is performed for the
next instruction after writing memory-mapped IC while
the ICE bit in CCR is set to 1.
0: Re-fetch is performed
1: Re-fetch is not performed

Renesas SuperH SH-4A Specifications

General

Brand	Renesas
Model	SuperH SH-4A
Category	Computer Hardware
Language	English