Renesas SuperH SH-4A - Page 452

Rev. 1.50, 10/04, page 432 of 448
Bit Bit Name
Initial
Value R/W Description
31 to 6  H'000000F R Reserved
The write value must be the initial value.
5 RABD 1 R/W Speculative execution bit for subroutine return
0: Instruction fetch for subroutine return is issued
speculatively. When this bit is set to 0, refer to
Appendix C, Speculative Execution for Subroutine
Return.
1: Instruction fetch for subroutine return is not issued
speculatively.
4  0 R Reserved
The write value must be the initial value.
3 INTMU 0 R/W Interrupt mode switch bit
0: SR.IMASK is not changed when an interrupt is
accepted.
1: SR.IMASK is changed to the accepted interrupt level.
2 to 0  All 0 R Reserved
The write value must be the initial value.