Rev. 1.50, 10/04, page 71 of 448
Exception Transition
Direction*
3
Exception
Category
Execution
Mode
Exception
Priority
Level*
2
Priority
Order*
2
Vector
Address Offset
Exception
Code*
4
Nonmaskable interrupt 3 — (VBR) H'600 H'1C0 Interrupt Completion
type
General interrupt request 4 — (VBR) H'600 —
Note: 1. When UBDE in CBCR = 1, PC = DBR. In other cases, PC = VBR + H'100.
2. Priority is first assigned by priority level, then by priority order within each level (the
lowest number represents the highest priority).
3. Control passes to H'A000 0000 in a reset, and to [VBR + offset] in other cases.
4. Stored in EXPEVT for a reset or general exception, and in INTEVT for an interrupt.
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