Rev. 1.50, 10/04, page 76 of 448
Instruction TLB Multiple Hit Exception:
• Source: Multiple ITLB address matches
• Transition address: H'A0000000
• Transition operations:
The virtual address (32 bits) at which this exception occurred is set in TEA, and the
corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates
the ASID when this exception occurred.
Exception code H'140 is set in EXPEVT, initialization of VBR and SR is performed, and a
branch is made to PC = H'A0000000.
CPU and on-chip peripheral module initialization is performed in the same way as in a manual
reset. For details, see the register descriptions in the relevant sections of the hardware manual
of the target product.
Data TLB Multiple-Hit Exception:
• Source: Multiple UTLB address matches
• Transition address: H'A0000000
• Transition operations:
The virtual address (32 bits) at which this exception occurred is set in TEA, and the
corresponding virtual page number (22 bits) is set in PTEH [31:10]. ASID in PTEH indicates
the ASID when this exception occurred.
Exception code H'140 is set in EXPEVT, initialization of VBR and SR is performed, and a
branch is made to PC = H'A0000000.
CPU and on-chip peripheral module initialization is performed in the same way as in a manual
reset. For details, see the register descriptions in the relevant sections of the hardware manual
of the target product.
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