RFL 9300 RFL Electronics Inc.
February 7, 2000 13 - 3 (973) 334-3100
13.3 THEORY OF OPERATION
The RFL 93B CC controls all communications between one RFL 9300 and another. A block diagram of the RFL
93B CC appears in Figure 13-3.
13.3.1 OVERVIEW
The RFL 93B CC Communications Controller Module contains a 16-bit microcontroller that works with dedicated
logic circuits. These circuits work together to regulate all messages sent from one RFL 9300 to another. The
communications can be any one of the following:
1. 7.2-Kbps data over a modem, such as the RFL 93B MO Modem Module.
2. 56-Kbps or 64-Kbps data using a direct digital interface, such as the RFL 93 DD module.
3. 56-Kbps or 64-Kbps data over fiber optic cables, using a RFL 93 FT/FR fiber optic module.
During turn-on, the RFL 93B CC module learns the RFL 9300's communication configuration. It does this by
measuring the clock rate, testing control lines, and reading the strap settings on the RFL 93B SV Supervisor
Controller Module. The RFL 93B CC does not have any strap settings for different communication configura-
tions. Its software switches internally, depending on the system's communication configuration and data rate.
Those functions that are common to all communication configurations and speeds will be described first; more
specific configurations will be described later.
Messages can originate in any one of seven modules within the system. Most messages pass through the RFL
93B SV Supervisor Module to the RFL 93B CC module by way of an eight-bit bus. When a message arrives, the
microcontroller establishes its priority and stores it in the microcontroller's internal RAM. If the message contains
time values, the microcontroller increments the time and erases the message if overflow occurs before the mes-
sage can be sent.
The microprocessor compresses the message with the highest priority and loads it into the transmitter shift reg-
isters, along with CRC bits. The RFL 93B CC module at the remote RFL 9300 will use the CRC bits to test the
message when it receives it. All messages between RFL 9300's are sent synchronous and serial. The simplest
messages consist of single fifteen-bit word; the most complicated requires two fifteen-bit words. Each word con-
tains eight data bits and six CRC bits.
The transmitter logic circuits insert a frame bit to mark the beginning of each word. This bit toggles from one
group of data and CRC bits to the next group of data and CRC bits. Words are continually sent, even if there is
nothing to communicate; null words fill in the voids. By always sending valid words, the remote RFL 9300 can
frame, regardless of the state of the transmitting RFL 9300. Incoming words pass through the receiver shift reg-
isters, where a comparator and EPROM look-up table combine to test the CRC security of each word. The se-
curity test is done in hardware because of the high speeds possible with 56 or 64-Kbps communication.
The microcontroller frames the data by resetting a fifteen-state counter when the data, CRC, and frame bits line
up. The counter then automatically generates a latch signal for future data reads by the microcontroller. After
the microcontroller accepts a valid secure word, it translates and expands it into a message. The message usu-
ally passes to the RFL 93 SV module for distribution to other modules in the system.
After two RFL 9300's establish a bi-directional communication link, each unit measures the average one-way
channel delay. This delay, called "CDC-P" (channel delay compensation - ping-pong), is passed on to the su-
pervisor. The RFL 93B CC module continually monitors the channel delay, and reports any significant changes
to the supervisor.
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