17.5 THEORY OF OPERATION
17.5.1 OVERVIEW
The RFL 93B FT/FR Single Width Fiber Optic Transceiver module converts a single RS-422 data input into an
FSK type signal, suitable for transmission over a fiber optic cable. The receive portion of the module accepts
FSK signals from the fiber optic receiver and converts them back to RS-422 signals. The module consists of
RS-422 drivers and receivers, buffers, a crystal oscillator, a voltage reference, a VF converter and an FPGA. A
block diagram of the module is shown in Figure 17-3, and a schematic diagram is shown in Figure 17-4.
17.5.2 TRANSMIT DESCRIPTION
The crystal oscillator U7 provides a 3.584 mHz clock to pin 43 “OSC” input of the FPGA 1010B. The signal is
divided down to 128 kHz for 64Kbit operation, and 112 kHz for 56Kbit operation. Jumper J2 enables the user to
make the selection. Since the 64Kbit and 56Kbit operation is similar, only the 64Kbit operation will be discussed.
The 128Khz signal becomes the clock input for a pair of D flip-flops connected to provide 64K and 32K timing
signals. The 64K signal is brought out to become the TX_CLK on U1 pin 9, converted to RS-422, and will be the
local clock source for TX_DATA originating from the 93B CC module.
The FPGA 64K and 128K signals are routed to an internal data selector that selects 64K when TX_DATA is a
logic 1, and 128K when TX_DATA is a logic 0. A group of four internal D flip-flops are clocked by the 128K sig-
nal while the 32K inverted and 32K non-inverted signals control their PRESET inputs. The two signals created
are DIS1Q and DIS2Q. These two signals control a group of four internal AND gates that route the output of the
data selector to the “SEND_DAT” FPGA 1010B pin 36.
17.5.3 RECEIVE DESCRIPTION
The RECEIVE_DATA signal from the LIB (Light Interface Board) enters the board and is buffered by U3. This is
a composite TTL signal containing modulated data an RX clock. The signal is demodulated and the clock is re-
covered by the following PLL (Phase Lock Loop) circuit. The circuit is composed of individual integrated circuits
in order to achieve the stability required for this application.
Exclusive OR gate U6 section A is the phase detector, and R4, R6, R7, C8 and C9 filter the phase detector out-
put. V/F converter and associated components form the VCO. A precision voltage reference U4 provides bias
and VCC to the phase detector. Internal D flip-flops and logic are located in the FPGA U10. The demodulated
data, RCVD_DAT and recovered clock, RCVD_CLK signals are routed from the FPGA U10 to the RS-422
transmitter U1.
17.5.4 RECEIVE CLOCK ERROR DETECTION
The FPGA, U10 contains logic to detect problems with the recovered clock signal. In the event the recovered
clock signal is lost for more than 50 microseconds the CS_DET output will pulse high for 4 milliseconds. If the
clock has returned prior to the end of the 4 millisecond period CS_DET will go low. If the clock is still inactive at
the end of the 4 millisecond time period CS_DET will remain high until the clock returns. This circuit will also
detect a slipped clock cycle by comparing the recovered clock to the local crystal generated Tx clock. Although
they are asynchronous, the two clocks have alternating clock edges. If either clock has two rising edges without
a rising transition of the other, CS_DET will go high for 4 milliseconds. The CS_DET signal is inverted and buff-
ered by U8 and is routed to the Communication Controller module.
17.5.5 HOT STANDBY OPERATION
Hot Standby operation consists of one Communications Controller card and two Fiber Optic transceivers. This
mode of operation provides for redundant fiber paths. The logic for switching between primary and secondary
fiber paths is performed in the FPGA, U10. A control signal for switching the fiber paths originates from CC#1
and signals are routed via the backplane. See Figure 17-4 for the signal routing diagram.
RFL 9300 RFL Electronics Inc.
May 1, 1998 17 - 6 (973) 334-3100
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