RFL Electronics RFL 9300 - Figure 13-6. Logic Diagram for Programmable Logic Device U24

LOW IF 60,62 64,66 A0,A2 A4 HEX
01111X0X LOW IF
OR
01111X1X HIGH IF LATCH
011111XX 011110XX LOW IF HIGH IF LATCH
OR
LOW IF 66 HEX
64 HEX LOW IF A4 HEX LOW IF 62,A2 LOW IF 60,A0 LOW IF
HEX HEX
PIN 1 PIN 2 PIN 3 PIN 4 PIN 5 PIN 6 PIN 7 PIN 8 PIN 9 PIN 11
/WRITE STROBE /READ STROBE
A7 A6 A5 A4 A3 A2 A1 A0
PIN 19
/WR /WR /RD
WHEN LOW CAUSES MICROCONTROLLER TO TAKE 3 WAIT STA
T
/WAIT
PIN 18
ALARM
PIN 17
STANDBY
PIN 16
/TX_MSB
PIN 15
/TX_LSB
PIN 14
/RX_IN
PIN 13
/SUP_COM
PIN 12
/MODEM
ALARM LINE TO SUPERVISOR,HIGH IF ALARM LOW IF /WR WHILE ADDRESS = 011110XX /TX MSB STROBE /TX MSB STROBE /RX STROBE LOW WHILE READING OR WRITING TO SUPERVISOR BU
S
LOW WHILE READING OR WRITING TO THE MODEM BUS
HIGH Z IF /WR WHILE ADRESS = 011111XX USED TO LATCH MSB OF TXWORD IN SHFT REG USED TO LATCH LSB IF TX WORD IN SHT REG USED TO READ LATCHED DATA INTO U17 PORT 0
/SELECT SUPERVISOR BUS
/SELECT MODEM BUS
A7 - A0 A7 - A0 A7 - A0 A7 - A0 A7 - A0 A7 - A0 A7 - A0 A7 - A0
/WR
/RD A15 A14 A13 A12 A11 A10 A9
A8
M
S
B
O
F
8 0
C
1
9 6
K
C
A
D D
R
E
S S
Figure 13-6. Logic diagram for programmable logic device U24
RFL 9300 RFL Electronics Inc.
February 7, 2000 13 - 10 (973) 334-3100