RFL 9300 RFL Electronics Inc.
October 29, 2001 2 - 30 (973) 334-3100
2.11 OSCILLOGRAPHY BOARD
The Oscillography Board is an extension of the display controller. It is directly connected to the display controller
through an 8-bit bi-directional data bus and additional control lines. When a trip event occurs, the oscillography
board will record and store ten cycles of all four measured trip currents as well as the trip output signals. Five
cycles of pretrip and five cycles of post trip information will be saved. The four current signals are read by an 8-
bit analog to digital converter and kept in a rolling buffer by the controller. In the event of a trip, the buffer is time
tagged and a new buffer will be opened.
Five buffers are available to store oscillography data for five of the most recent trip events. Section 6 of this
manual describes how the oscillography data can be accessed.
The oscillography board also holds the alarm annunciator.
The trip signals that originate on the phase controller modules and the DTT signal from the RFL 93B SV termi-
nate on the Oscillography Board. These signals are applied to a programmable logic chip along with various
control signals originating on the display controller and Relay I/O module. The combination logic circuit pro-
grammed into this chip insures that once issued, the trip signals applied to the output relays remain latched until
released by the display controller. If the display controller disables trip, the trip signals have no effect.
2.12 IRIG-B
The RFL 9300 has the ability to synchronize its internal real time clock with an external IRIG-B clock source.
The IRIG-B signal enters the RFL 9300 via a BNC connector on the Relay I/O module. The signal is then routed
to the oscillography board, which demodulates the IRIG-B signal and feeds it to an embedded controller, which
is also used for the oscillography feature. The controller updates its battery operated real time clock based on
the received IRIG-B signal. In the absence of IRIG-B, the APRIL setting of the display clock will be used. IRIG-B
is only used for time stamping alarm and trip events.
2.13 DIAGNOSTICS
Various diagnostic routines are continuously being executed while the RFL 9300 is operating. These include the
following:
1. During normal program execution, a different programmed variable is tested and then passed to all
phase controllers at 4-second intervals. This means each controller will have its programmed variables
refreshed once every 32 seconds. The display controller also stores a copy of these variables but the
"official" copy resides on the RFL 93B SV.
The display controller also refreshes its stored programmed variables at 32-second intervals by re-
questing a different variable from the RFL 93B SV every 4 seconds.
2. Periodically, each phase controller passes a parallel bus test request message (55H) to the RFL 93B
SV. The RFL 93B SV must return a response message (AAH) within a preset time limit or the test will
fail. The RFL 93B SV executes the same test with all phase controllers in the opposite direction. The
only difference is that the RFL 93B SV will alarm if any one of the phase controllers does not respond
properly. The phase controller alarm applies only to the controller conducting the test.
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