RFL 9300 RFL Electronics Inc.
October 29, 2001 2 - 12 (973) 334-3100
2.6 AUXILIARY CURRENT TRANSFORMER (ACT)
A separate RFL 93B PC Phase Controller and RFL 93B ACT I/O monitors each phase current and the ground
or 3I
0
current. The input to the RFL 93B ACT I/O consists of a small toroidal core with a single turn looped
through its center. This single turn is an extension of the secondary winding of the CT supplying the phase cur-
rent waveform. Like most static relays, the burden presented by the RFL 93B ACT I/O is in the milliohm range.
An active circuit cancels out the flux in the toroidal core. This allows the toroid to handle large dc offsets without
saturating. The circuit maintains its accuracy over a 250-ampere (rms) dynamic range.
The RFL 93B PC detects disturbances in the phase current waveform received from the RFL 93B ACT I/O. It
generates a signal in response that prevents a charge from accumulating on the feedback capacitor in the RFL
93B ACT I/O's feedback control circuit. This patented procedure prevents any dc offsets that may be present in
the current waveform from saturating the core.
2.7 PHASE CONTROLLERS
Once the phase controllers have initialized, they begin to monitor system current and execute the protection
algorithms. The leading edge of the 2-kHz system clock supplied by the RFL 93B SV synchronizes phase con-
troller program execution. All background and foreground routines execute during the 0.5-ms system clock in-
terval. The phase controllers execute the CCS trip algorithms listed below. Except for DTT (which is controlled
by the RFL 93B SV module), the individual RFL 93B PC modules make all trip/no trip decisions.
Phase Controller operation differs radically depending on whether the relay is configured for 2-terminal or 3-
terminal operation:
2-Terminal Operation:
a. Phase Controllers execute their trip algorithms based on true CT current values.
b. Trip algorithms are executed immediately upon receiving a CCD, WCM or UHST message from the remote
station.
3-Terminal Operation:
a. The system clock supplied by the supervisor is phase locked to the line current waveform (if one exists) on
the basis of error signals supplied by whichever phase controller is currently selected by the 93B SV. The
phase controller measures the number of clock signals received over a defined interval and signals the su-
pervisor to adjust the period of the system clock until it is receiving exactly 33 clock signals per line fre-
quency period.
b. Phase Controllers, with the exception of the 3I0 controller, execute their trip algorithms based on transient
CT current values obtained by subtracting prefault load current from true CT current on a continuous basis.
This is done to counteract the wide phase angle swings encountered in 3-terminal systems. 3I0 controller
trip algorithm execution, is based on true CT current, the same as in 2-terminal applications.
c. Trip algorithms are not executed until a CCD, WCM or UHST message is received from both remote sta-
tions. In addition, before the messages are accepted they must “validate” each other i.e. they must, with a
high degree of certainty, represent the total remote station CT transient current during the same time inter-
val.
d. Once this “validation” process is complete, the remote station composite transient CT current value and the
local station CT current transient value are run through the same trip algorithms used for 2-terminal sys-
tems.
In 2-terminal systems the analog output of each RFL 93B ACT I/O is passed to an RFL 93B PC Phase Control-
ler Module. The RFL 93B PC uses an equivalent 10-bit serial A/D converter to convert the analog signal to a
digital value. The integral of all such “control” CT current samples taken during a half-cycle is computed when
the half-cycle-ending zero-crossing time-tag is recorded.
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