24.3 THEORY OF OPERATION - HARDWARE
For the following discussion, refer to Figures 24-3 and 24-7.
24.3.1 SYSTEM OVERVIEW
The Single Pole Chassis receives phase specific trip command signals from the 9300 back plane. If the unit is
programmed to be in the single pole mode, phases A, B or C can trip independently of the other two phases. If
the unit is programmed to be in the three pole mode and any one phase has a trip command, all three phases
will trip simultaneously. Each phase (A, B and C) has six “form A” relays that are energized if a trip is active and
if the global trip disable is inactive. Trip release will occur based on any one of the following three trip release
options:
1. Trip signal no longer received and no dc trip coil current sensed.
2. Trip signal no longer received.
3. 100ms after trip signal no longer received.
The trip release options are programmed into the Display Controller and downloaded to the Single Pole Chassis
during system initialization. The Single Pole Chassis is disabled and the trip disable LED is on until the first valid
download has been received from the display controller.
One of the trip release options will latch the trip relays until the dc trip coil current drops below 100ma. Two trip
relays for each phase have associated sense current capability. The other two trip release options will open the
relays regardless of current sense after the trip command is no longer active. One option has no delay to re-
lease and the other option will release after a delay of 100 ms. If the sense current relays are active when there
is no trip or if the sense current is on for more than 500ms, a current sense alarm signal (alarm #27) is passed
to the supervisor. The supervisor look for changes in the target data and alarm status. When a change is de-
tected, the supervisor sends the alarm status and target information to the display controller. When a trip is ac-
tive or if current is sensed in either of the two relays, the trip and or sense indications are latched into the front
panel LEDs of the Single Pole Chassis. These LEDs will remain on even after the trip clears and the sense cur-
rent goes to zero. When the unit is turned off and then back on again, the old trip target and current sense in-
formation is downloaded to the Single Pole Chassis from the Display controller and again the LEDs remain on.
This download process uses 2 wires for loading the old target information, single pole/three pole and trip re-
lease modes. Resetting the LED targets occurs when the display controller downloads target information with a
value of zero. With each download, the Single Pole Chassis initiates a three second LED test where all the
LEDs are turned on. After three seconds has expired, the target information downloaded from the display con-
troller is shown on the panel.
The supervisor monitors the operational condition of the Single Pole Chassis. The target and alarm status as
well as the trip release codes are passed to the supervisor every 264 ms. This is an indication to the supervisor
that the Single Pole Chassis is present and the alarms are off. Each of the phases acts independently. The de-
scription below will be for phase A.
24.3.2 TRIP OPERATION
The trip inputs from the phase controllers are a normal high on the 9300 back plane. When the trip becomes
active JP1-1 and A_IN go low. If trip disable is also low, a trip signal will go high out of A_TR1. Trip disable will
block a trip inside the Actel and through the circuitry associated with TRIP_DIS_OUT. If TRIP_DIS_IN is low,
TRIP_DIS_OUT is also low. This turns on Q1 and Q2 which activates relay K1. This supplies power to the trip-
ping relays K3 - K8, K11 - K16 and K19 - K24. Associated with each phase group of relays is a capacitor. For
phase A, C14 will be charged up by the +15 Volt supply. If a trip becomes active the relays are energized, and
C14 provides the energy to pull in the relays in less than 4ms. When the relays are energized, the voltage on
C14 decreases because of the drop across R11, R12 and R66. This lowers the steady state drain on the +15
Volt supply without affecting the operate speed of the relays. A debounce delay is created in the Actel between
the A_IN signal and the A_TR1 trip output signal. This delay is from .5 to 1 ms. This results in a total trip delay
of less than 5 ms.
RFL 9300 RFL Electronics Inc.
August 25, 2000 24 - 6 (973) 334-3100
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