RFL 9300 RFL Electronics Inc.
February 7, 2000 13 - 6 (973) 334-3100
13.3.2 HARDWARE DESCRIPTION
13.3.2.1 WATCHDOG RESET FUNCTION
The RFL 93B CC module contains a 16-bit microcontroller (U18). U18 must be reset during turn-on or if the in-
ternal software program counter causes a program jump to a wrong location. Watchdog timer U30 pulls U18-7
(/RESET) if there are no transitions into U18-6 (WDI) for 1.6 seconds; this causes a reset. U30 also will assert a
low on U18-7 for at least 50 ms if the voltage into U30-2 (Vcc) falls below 4.65 volts. In the software, each rou-
tine toggles a test bit internal to U18. After all routines have successfully executed and the test bits are correct,
the port 2.6 line out of U18 toggles. This pushes back the 1.6-second timer inside U30. U30-7 also connects to
the transmitter shift registers (U13-10 and U14-10). Zeroes are forced out of the shift register; these are invalid
word that prevent old or extraneous messages from being sent.
13.3.2.2 TRANSMITTER CIRCUIT
A timing diagram for the RFL 93B CC's transmitter circuit appears in Figure 13-4.
Transmitter shift registers U13 and U14 are loaded with data and CRC bits through a software created bus lo-
cated on port 1 of microcontroller U18. U18 loads eight data bits out of port 1, and then writes them to address
location 6600H. This causes pin 16 on programmable logic device U24 to strobe low. This is fed to U14-12,
latching the data into U14. Next, the CRC bits are loaded into port 1 U18 and written into address location
6400H. This causes U24-15 to strobe low, latching the CRC into U13. U9 and U15 form a fifteen-state counter.
During each TX CLOCK negative edge, a bit is shifted out of the transmitter shift and the counter is incre-
mented. On the fifteenth count, a frame bit stored at U12-12 toggles and passes through U16-1. This creates
the word pattern of a toggled frame bit followed by eight data bits and then six CRC bits followed by another
toggled frame bit. Two interrupt lines come from the fifteen-state counter and connect to U18-25 and U18-26.
If the data rate is high (56 or 64 Kbps), a negative edge on U18-25 will cause U18 to enter the transmitter inter-
rupt routine. If the data rate is low (7.2 Kbps), a positive edge on U18-26 will cause U18 to enter the transmitter
interrupt routine. The RFL 93B CC selects the interrupt pin to use during turn-on, when it learns the communica-
tion configuration. There are two different interrupt lines because U18 needs more lead time during 56-Kbps or
64-Kbps operation; the interrupt must service the shift registers before the end of the fifteenth pulse interval. If
nothing new is latched into the shift registers the same word and CRC bit combination repeats indefinitely until
another word/CRC bit combination is loaded. While framing the receiver, the same (null word) word is repeated.
This is done because framing requires the full use of the microcontroller for a five-word interval.
13.3.2.3 RECEIVER CIRCUIT
A timing diagram for the RFL 93B CC's receiver circuit appears in Figure 13-5.
The receiver logic hardware consists of shift registers U3 and U4, comparator U6, EPROM U5, a fifteen-state
counter formed from U8 and U9, and latches U7 and U12. When correctly framed, the frame bit plus eight data
bits are present on U5's address lines. The fifteen-state counter latches the data into U7 when U7-11 goes low.
The received CRC and trailing flag bit are also present on U6's "P" inputs. A look-up table in U5 contains the
valid matching CRC and trailing frame bit; the look-up value is present on U6's "Q" inputs. U6-19 goes low if the
CRC plus trailing frame bit matches the look-up code base on the received data and leading (opposite) frame
bit. This low signal is latched into U12 on U12-5 and fed to U18-17. The latch strobe also goes to the microcon-
troller U18-38, where an interrupt occurs on the low-to-high transition. U18 reads the data latched in U7 and
tests U18-17 (P2.1) to see if the data is valid during the processing of the word.
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