23.3.5 ACTEL DESCRIPTION
The Actel chip performs all of the digital processing required in the interface. The receive pulses from U2 are
non-return to zero pulses. The recovered RX 64 kHz clock from the phase lock loop is recover from the com-
bined non-return to zero data stream. The 64 kHz clock could be inverted out of the divider. If necessary, the
sync detector in the Actel inverts the clock. If J5 is set to “LOOP”, the recovered 128 kHz receive clock is used
for generating the TX signals. If J5 is set to “NORMAL”, the TX source comes from a TX PLL module within the
Actel. The TX PLL module always outputs a 128 kHz clock. The clock may be phase locked to the TX reference
input line or it could be free wheeling. The TX PLL module looks for transitions on the TX reference input and if
they are absent, the module outputs a centered 128 kHz signal. It is not pulled to the high or low end of the PLL.
The TX clock is then used to read the TX data from the communications card. The TX LOGIC module in the Ac-
tel then generates two outputs for the AMI G.703 transmitter, the positive and negative TX pulse signals. In ad-
dition, it also creates the local TX clock.
The TX PLL module will free wheel on the 3.584 mHz crystal clock to create the 64 kHz TX clock. If the refer-
ence clock is present, the TX PLL will add or subtract one 3.584 mHz clock pulse interval to the 64 kHz output
on every rising edge of every 32nd reference clock pulse. This results in a very limited pull range with very little
average jitter. This means that at the most, one correction of 279 ns will be added or subtract once every
500,000 ns, or one part in 1,792.
RFL 9300 RFL Electronics Inc.
February 7, 2000 23 - 5 (973) 334-3100
To Next Page
Loading...