1
2
3
45678910
11
10
9
8
12
13
3
4
5
6
2
1
19
18
17
16
15
14
13
12
1
11
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
1
11
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
1
11
2
3
4
5
6
7
8
9
1
2
1
3
1
4
1
5
1
6
1
10
1
9
1
8
1
7
1
7
1
9
1
8
1
2
1
6
1
5
1
4
1
3
A25
C24
A24
A23
C23
C22
A22
C21
A21
C19
A19
C18
C7
C26
C25
C16
A7
A17
C17
A18
A6
C6
C12
3
5
7
9
11
13
1
2
4
6
10
15
12
14
5
12
9
10
11
6
7
13
4
1
2
3
14
15
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
15
14
13
12
11
10
9
7
4
1
2
3
6
5
18
17
16
15
14
13
12
11
19
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
1
19
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
1
11
2
3
4
5
6
7
8
9
4
7
9
12
15
1
2
3
5
6
11
10
14
13
20 18 21
17
16
15
14
13
11
10
9
19
22
23
1
2
3
4
5
6
7
8
24 12
1
2345678910
20 10
2010
816
714
816
168
816
10
10
10
10
10
20
20
20
20
20
R15
R14
RZ6
U28
U28
U19
U18
U26
RZ7 RZ7
RZ5RZ5RZ5RZ5RZ5RZ5RZ5RZ5
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
U23
U29
U29
U20
U30
U27
U17
U16
U24
U25
C26
C28
C24
C25
C23
C30
C19
C18
C17
C29
C37
C16
C27
C20
C38
RZ9
HI-Z
HI-Z
WATCHDOG
WATCHDOG
ADR110
WRSTRB
ADR100
RAM
PCR/WEN
PCR/WEN
ALE/ADV
AD6
AD4
AD2
AD1
AD0
RD
WR
ADR101
COMM_EN
SUPER_RD
SUPER_RD
SUPR/W
SUPR/W
AD3
AD7
AD5
RESET
RESET
(WR)
(WR)
MEMADDR
COMM2WR
(RD)
(RD)
D0
D1
D2
D3
D4
D5
D6
D7
ADDRCLK
BLKADDR
COMM2ADR
TIMEREN
COUNT
TIMERERR
TIMERSTR
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
COMM2-ADDR
WRITE DATA EN
WR
CS
RD
INT-G
INT-C
INT-B
INT-A
SC READY
G SUP EN
C SUP EN
B SUP EN
A SUP EN
(INTERRUPT)
(C000H)
(A000H)
(8000H)
STATIC RAM
NON-VOLATILE
DATA BUS
LOCAL CONTROLLER
PHASE CONTROLLERS
INTERRUPT SIGNALS TO
TO PHASE CONTROLLERS
TRIP ENABLE/DISABLE SIGNALS
CONTROLLERS
COMMUNICATIONS
SIGNALS TO/FROM PHASE
PARALLEL PORT CONTROL
BUS
COMMUNICATIONS
BACKPLANE
45.3K
1K
10K
A
CLR
QD
QC
QB
QA
A
CLR
QD
QC
QB
QA
OC
C
1D
2D
3D
4D
5D
6D
7D
8D 8Q
7Q
6Q
5Q
4Q
3Q
2Q
1Q
OC
C
1D
2D
3D
4D
5D
6D
7D
8D 8Q
7Q
6Q
5Q
4Q
3Q
2Q
1Q
OC
C
1D
2D
3D
4D
5D
6D
7D
8D8Q
7Q
6Q
5Q
4Q
3Q
2Q
1Q
10K 10K
10K
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
1G
2G
1A1
1A2
1A3
1A4
2A1
2A2
Q
Q
REXT
CEXT
CLR
B
A
Q
Q
REXT
CEXT
CLR
B
A
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I9
I/CLK
I1
I2
I3
I4
I5
I6
I7
I8
G2
G1
C
B
A
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
GL
G
DIR
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
B5
B6
B7
B8
A5
A3
A4
A6
A7
A8
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
A1
A2
G1
G2
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q8D
7D
6D
5D
4D
3D
2D
1D
CP
OC
/BA
G
4Y
3Y
2Y
1Y
4B
4A
3B
3A
2B
2A
1B
1A
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
DQ7
CE
WE
DQ8
OE
.001uF
.001uF
10K
SHT 1)
(SHT 1)
(SHT 1)
SHT 1)
(SHT 1)
(SHT 1)
(SHT 1)
Figure 10- 4. Supervisor Controller module for
RFL 9300 Charge Comparison System
(Assembly No. 106300; Schematic No. D-106304-1-B)
Sheet 2 of 2
RFL 9300 RFL Electronics Inc.
September 10, 2007 32 -7 (973) 334-3100
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