RFL 9300 RFL Electronics Inc.
October 29, 2001 2 - 24 (973) 334-3100
2.7.8 EFFECT OF CHANNEL DELAY ON RFL 9300 PERFORMANCE
The RFL 9300 depends on accurate channel delay measurements for proper operation. Channel delay meas-
urement errors approaching +
3.5 ms can be tolerated without producing false trip signals. This is a vast im-
provement over previous current differential systems. Most existing systems have difficulty dealing with delays
that exceed 0.25 ms.
The "ping-pong" method of measuring channel delay has one basic limitation. If the sending and receiving paths
have different delays they will not be detected. The RFL 9300 uses a method based on the measurement of
zero crossings of the phase current waveforms to correct this. It is called "DML" (Delay Measurement based on
Load current). The locally stored half-cycle integral value that is compared with the received CCD value is se-
lected by time-tag comparison. The adjusted received time-tag must "nest" between the stored start and finish
time-tags of the local value.
The "nesting error" is computed by the Phase A Controller and passed to the RFL 93B SV. This shows how
close the adjusted time-tag comes to falling exactly half-way between the local start and finish time-tags. The
RFL 93B SV uses the nesting error to correct the channel delay measurement value. The corrected value is the
channel delay compensation (CDC) value that is distributed to all phase controllers. This correction is not made
if there are active fault detectors anywhere in the system or if the Phase A load current is less than 1 A
rms
.
This insures that system disturbances or line charging currents are not distorting the current waveform; this
would interfere with accurate zero-crossing measurements. CDC will detect transmit and receive path differ-
ences in the ping-pong measurement and correct them. Channel Delay Compensation is not available when the
relay is configured for 3-terminal operation. In this mode of operation the relay is working with transient CT con-
trol currents which will likely occur only when a fault detector is active.
Fault detectors are an integral part of the RFL 9300 system. Traditional relaying systems have used discrete
fault detector relays to supervise tripping. In the RFL 9300, software techniques detect phase current waveform
disturbances and supply the fault detector signals. Phase fault disturbances are noted by a lit LED indicator on
the front panel of the affected phase controller module. The fault detector algorithms are the same regardless of
whether the relay is configured for 2-terminal or 3-terminal operation i.e. they are based on true CT current
readings at all times.
All phase controllers execute a bias-control function to protect against false-tripping caused by line-charging
current during breaker turn-on. The function is enabled through the key pad. Bias control protection is provided
for a maximum of 1 second from the time that breaker closing is detected. The duration of the protection is pro-
grammable through the key pad in 50-ms steps, up to a maximum of 1 second. This is shown in Figure 2-6.
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