ST STM32F10 Series User Manual

Interrupts and events UM0306
104/519
Interrupt mask register (EXTI_IMR)
Address Offset: 00h
Reset value: 0000 0000h
Event mask register (EXTI_EMR)
Address Offset: 04h
Reset value: 0000 0000h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved MR18 MR17 MR16
rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8 MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:19 Reserved, must be kept at reset value (0).
Bits 18:0
MRx: Interrupt Mask on line x
0: Interrupt request from Line x is masked
1: Interrupt request from Line x is not masked
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved MR18 MR17 MR16
rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8 MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:19 Reserved, must be kept at reset value (0).
Bits 18:0
MRx: Event Mask on line x
0: Event request from Line x is masked
1: Event request from Line x is not masked
www.BDTIC.com/ST

ST STM32F10 Series Specifications

General

Series	STM32F10
Core	ARM Cortex-M3
Operating Frequency	Up to 72 MHz
Flash Memory	16 KB to 1 MB
SRAM	4 KB to 96 KB
GPIO Pins	Up to 80
ADC Resolution	12-bit
Number of ADCs	Up to 3
Operating Voltage	2.0 V to 3.6 V
DAC Resolution	12-bit
Communication Interfaces	I2C, SPI, USART, USB
Operating Temperature	-40°C to +85°C
Package Options	LQFP, BGA
Number of DACs	Up to 2 (some devices)