Advanced control timer (TIM1) UM0306
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For example, to configure the up-counter to count each 2 rising edges on ETR, use the
following procedure:
1. As no filter is needed in this example, write ETF[3:0]=0000 in the TIM1_SMCR register.
2. Set the prescaler by writing ETPS[1:0]=01 in the TIM1_SMCR register
3. Select rising edge detection on the ETR pin by writing ETP=0 in the TIM1_SMCR
register
4. Enable external clock mode 2 by writing ECE=1 in the TIM1_SMCR register.
5. Enable the counter by writing CEN=1 in the TIM1_CR1 register.
The counter counts once each 2 ETR rising edges.
The delay between the rising edge on ETR and the actual clock of the counter is due to the
resynchronization circuit on the ETRP signal.
Figure 49. Control circuit in external clock mode 2
12.4.5 Capture/compare channels
Each Capture/Compare channel is built around a capture/compare register (including a
shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and
an output stage (with comparator and output control).
Figure 50 to Figure 53 give an overview of one Capture/Compare channel.
The input stage samples the corresponding TIx input to generate a filtered signal TIxF.
Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be
used as trigger input by the slave mode controller or as the capture command. It is
prescaled before the capture register (ICxPS).
COUNTER CLOCK = CK_CNT = CK_PSC
COUNTER REGISTER
35 3634
ETR
CNT_EN
f
CK_INT
ETRP
ETRF
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